The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metalization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising of at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques and filling the opening with conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher-k values. Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Hence, a feature formed in a low k dielectric layer may be damaged when the photoresist mask used to form the feature (e.g., trench or via) is removed.
Other problems that have been observed when working with low k materials is that of via poisoning and resist scumming. For example, via poisoning may be observed after the formation of a via in a low k dielectric layer and the subsequent formation and patterning in the photoresist that forms the trench mask. The via poisoning may cause a mushroom shape of resist to form at the top of the via hole, and resist scum may be seen at the surface of the dielectric layer in the mask opening. An example of this is depicted in FIG. 1. A substrate 10, which may be a conductive material such as copper, is covered by a bottom etch-stop layer 12, which can be made of silicon nitride, for example. The low k dielectric layer 14 has been formed on the bottom etch stop layer 12. A cap layer 16, formed from silicon oxide, for example, covers the low k dielectric layer 14. The via hole 20 was previously formed in the low k dielectric layer 14. Upon deposition and patterning of the photoresist material 18, the mushroom shape 22 is observed due to the via poisoning. It is thought that the photoresist deposition and patterning process produces outgassing from the low k dielectric layer 14 to produce mushroom feature 22 and resist scum 24 within the trench pattern opening 26.
The outgassing prevents the resist from properly getting into the via hole 20 so that it piles up on top of the via hole 20. This outgassing problem leads to improperly formed topology on the wafer. The resist around the via hole 20 becomes very thick and difficult to pattern. When attempts are made to pattern and expose it, that area can not be exposed properly.
Attempts have been made to mitigate the via poisoning and resist scumming problem. One of these is to provide a baking step before the formation of the trench mask layer. Although this has been seen to help the via poisoning problem, it does not substantially eliminate the problem. Other methodology that has been attempted is to provide spin-on organic BARC in the via, but the relatively low adhesion of this material to the via sidewalls and bottom has caused this approach to fail in substantially eliminating via poisoning concerns. Another method to eliminate via poisoning concerns is to provide a thick layer of oxide within the via, but this has the disadvantage of undesirably reducing the via size. Other attempts have included depositions of relatively thick layers of organic and inorganic BARCs within and on top of the via, but such attempts have the undesired effect of requiring a photoresist layer substantially as thick as the BARC layer.
The photoresist masks for forming the via and trench are typically deposited at a thickness of 5000 A or more. Such a thickness is undesirably large, resulting in less accurate patterning than that achievable with a relatively thinner photoresist layer. However, such a large thickness is needed to account for photoresist consumption during patterning and etching and to protect the underlying dielectric layers. The introduction of any additional layers underneath the photoresist masks to allow for reduction of the photoresist layer thickness should not, however, have the undesirable side effects of increasing processing time and costs or increasing the likelihood of damage to underlying layers of materials.
There is a need, therefore, for a method for formation of an interconnect structure that can reduce the thickness of a photoresist layer in an economical manner that also maintains the integrity of the dielectric layer in which a via and trench are formed.